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| ? semiconductor components industries, llc, 2009 july, 2009 ? rev. 6 1 publication order number: mc44605/d mc44605 high safety, latched mode, greenline pwm controller for (multi) synchronized applications the mc44605 is a high performance current mode controller that is specifically designed for off ? line converters. this circuit has several distinguishing features that make it particularly suitable for multisynchronized monitor applications. the mc44605 synchronization arrangement enables operation from 16 khz up to 130 khz. this product was optimized to operate with universal mains voltage, i.e., from 80 v to 280 v, and its high current totem pole output makes it ideally suited for driving a power mosfet. the mc44605 protections enable a well ? controlled and safe power management. four major faults while detected, activate the analogic counter of a disabling block designed to perform a latched circuit output inhibition. features ? this is a pb ? free device* current mode controller ? current mode operation up to 250 khz output switching frequency ? inherent feed forward compensation ? latching pwm for cycle ? by ? cycle current limiting ? oscillator with precise frequency control ? externally programmable reference current ? secondary or primary sensing (availability of error amplifier output) ? synchronization facility ? high current totem pole output ? v cc undervoltage lockout with hysteresis ? low output dv/dt for low emi radiations ? low startup and operating current safety/protection features ? soft ? start feature ? demagnetization (zero current detection) protection ? overvoltage protection facility against open loop ? eht overvoltage protection (e.h.t.ovp): detection of too high synchronization pulses ? winding short circuit detection (w.s.c.d.) ? limitation of the maximum input power (m.p.l.): calculation of input power for overload protection ? overheating detection (o.h.d.): to prevent the power switch from an excessive heating latched disabling mode ? when one of the following faults is detected: eht overvoltage, winding short circuit (wscd), a too high input power (m.p.l.), power switch overheating (o.h.d.), an analogic counter is activated ? if the counter is activated for a time that is long enough, the circuit gets definitively disabled. the latch can only be reset by making decrease the v cc down to about 3.0 v, i.e., practically by unplugging or turning off the smps. *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. device package shipping ordering information pdip ? 16 p suffix case 648 1 marking diagram a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package pin connections 116 13 12 11 10 9 2 3 4 5 6 7 8 (top view) v cc v c output overheating detection current sense input demagnetization detection input r ref sync and ehtovp input gnd max power limitation osc capacitor (c t ) soft-start input disabling block (c ext ) error amp output 15 14 voltage feedback input wscd* program *winding short circuit detection MC44605P awlyywwg 1 16 MC44605Pg pdip ? 16 (pb ? free) 25 units/rail http://onsemi.com
mc44605 http://onsemi.com 2 block diagram + ? pwm q reset set latch supply management error 3 2 1 4 initialization reference 16 buffer demagnetization 8 10 oscillator 9 12 14 13 15 11 5 amp current sense over voltage management 7 6 v c output gnd wscd demagnetization detection input thermal shutdown synchronization and ehtovp c ext voltage feedback input e/a output maximum power over current soft ? start mc44605 v cs v cc enable uvlo1 uvlo2 v ref v cc r ref v demag out uvlo1 uvlo2 18 v i ref v ref v ref i ref v cc enable v cc enable v cc dis block c t limitation heating detection input programmation block out output v dt v s v shift level programmation soft ? start i ref input o.h.d. block v shift mpl block 2 dis out dis ohd dis mpl v wscd e.h.t.ovp block disabling block v cc sf w.s.c.d* comparator sense v cs v cs i sense dis mpl dis ohd sf i sense *w.s.c.d. = winding short circuit detection input mc44605 http://onsemi.com 3 maximum ratings rating pin # symbol value unit total power supply and zener current (i cc + i z ) 40 ma output supply voltage with respect to ground 2 1 v c v cc 18 v output current source sink 3 i o(source) i o(sink) ? 750 750 ma output energy (capacitive load per cycle) w 5.0 j soft ? start v ss ? 0.3 to 2.2 v v current sense, voltage feedback, e/a output, c t , r ref , mpl, ohd, c ext , wscd v in ? 0.3 to 5.5 v v e.h.t.ovp, sync input current ma source 9 6 i sync (source) i eht (source) ? 4.0 sink 9 6 i sync (sink) i eht (sink) 10 demagnetization detection input current source sink 8 i demag ? ib (source) i demag ? ib (sink) ? 4.0 10 ma error amplifier output sink current 13 i e/a (sink) 20 ma power dissipation and thermal characteristics maximum power dissipation at t a = 85 c thermal resistance, junction ? to ? air p d r ja 0.6 100 w c/w operating junction temperature t j 150 c operating ambient temperature t a ? 25 to +85 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. electrical characteristics (v cc and v c = 12 v, r ref = 10 k , c t = 2.2 nf, for typical values t a = 25 c, for min/max values t a = ? 25 to +85 c unless otherwise noted.) (note 1) characteristic pin # symbol min typ max unit output section (note 2) output voltage (note 3) low level drop voltage (i sink = 100 ma) (i sink = 500 ma) high level drop voltage (i source = 200 ma) (i source = 500 ma) 3 v ol v oh ? ? ? ? 1.0 1.4 1.5 2.0 1.2 2.0 2.0 2.7 v output voltage during initialization phase v cc ? 0 to 1.0 v, i sink = 10 a v cc ? 1.0 to 5.0 v, i sink = 100 a v cc ? 5.0 to 13 v, i sink = 1.0 a 3 v ol ? ? ? ? 0.1 0.1 1.0 1.0 1.0 v output voltage rising edge slew ? rate (c l = 1.0 nf, t j = 25 c) dvo/dt ? 300 ? v/ s output voltage falling edge slew ? rate (c l = 1.0 nf, t j = 25 c) dvo/dt ? ? 300 ? v/ s 1. adjust v cc above the startup threshold before setting to 12 v. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 2. no output signal when the error amplifier output is in low state, i.e., when for instance, v fb = 2.7 v. 3. v c must be greater than 5.0 v. mc44605 http://onsemi.com 4 electrical characteristics (v cc and v c = 12 v, r ref = 10 k , c t = 2.2 nf, for typical values t a = 25 c, for min/max values t a = ? 25 to +85 c unless otherwise noted.) (note 4) characteristic pin # symbol min typ max unit error amplifier section voltage feedback input (v e/a out = 2.5 v) 14 v fb 2.4 2.5 2.6 v input bias current (v fb = 2.5 v) 14 i fb ? ib ? 2.0 ? 0.6 ? a open loop voltage gain (v e/a out = 2.0 v to 4.0 v) a vol 65 70 ? db unity gain bandwidth t j = 25 c t a = ? 25 to +85 c bw ? ? ? ? ? 5.5 mhz voltage feedback input line regulation (v cc = 10 v to 15 v) v fbline ? reg ? 10 ? 10 mv output current sink (v e/a out = 1.5 v, v fb = 2.7 v) t a = ? 25 to +85 c source (v e/a out = 5.0 v, v fb = 2.3 v) t a = ? 25 to +85 c 13 i sink i source 2.0 ? 2.0 12 ? ? ? 0.2 ma output voltage swing high state (i e/a out (source) = 0.5 ma, v fb = 2.3 v) low state (i e/a out (sink) = 0.33 ma, v fb = 2.7 v) 13 v oh v ol 5.5 ? 6.5 1.0 7.5 1.1 v current sense section maximum current sense input threshold (v feedback (pin14) = 2.3 v and v soft ? start (pin11) = 1.2 v) 7 v cs ? th 0.96 1.0 1.04 v input bias current 7 i cs ? ib ? 10 ? 2.0 ? a propagation delay (current sense input to output at v th of mos transistor = 3.0 v) t plh(in/out) ? 120 200 ns oscillator and synchronization section frequency (t a = ? 25 to +85 c) f osc 16 ? 20 khz frequency change with voltage (v cc = 10 v to 15 v) f osc / v ? 0.05 ? %/v frequency change with temperature (t a = ? 25 to +85 c) f osc / t ? 0.05 ? %/ c ratio charge current/reference current (t a = ? 25 to +85 c) i charge /i ref 0.39 ? 0.48 ? free mode oscillator ratio = i discharge /(i discharge + i charge ) d 72 75 78 % synchronization input threshold voltage 9 v syncth ? 250 ? 200 ? 150 mv negative clamp level (i syncth ? in = 2.0 ma) neg ? sync ? 0.65 ? 0.5 ? 0.34 v undervoltage lockout section startup threshold 1 v stup ? th 13.6 14.5 15.4 v disable voltage after threshold turn ? on (uvlo 1) (t a = ? 25 to +85 c) 1 v disable1 8.3 ? 9.6 v disable voltage after threshold turn ? on (uvlo 2) (t a = ? 25 to +85 c) 1 v disable2 7.0 7.5 8.0 v 4. adjust v cc above the startup threshold before setting to 12 v. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. mc44605 http://onsemi.com 5 electrical characteristics (v cc and v c = 12 v, r ref = 10 k , c t = 2.2 nf, for typical values t a = 25 c, for min/max values t a = ? 25 to +85 c unless otherwise noted.) (note 5) characteristic pin # symbol min typ max unit reference section reference output voltage (v cc = 10 v to 15 v) 16 v ref 2.4 2.5 2.6 v reference current range (i ref = v ref /r ref , r = 5.0 k to 25 k ) 16 i ref ? 500 ? ? 100 a reference voltage over i ref range v ref ? 40 ? 40 mv demagnetization detection section (note 6) demagnetization detect input demagnetization comparator threshold (v pin9 decreasing) propagation delay (input to output, low to high) input bias current (v demag = 65 mv) 8 v demag ? th t plh(in/out) i demag ? lb 50 ? ? 0.5 65 0.5 ? 80 ? ? mv s a minimum off ? time when the pin 8 is grounded t dem ? gnd 1.5 3.0 4.5 s negative clamp level (i demag = ? 2.0 ma) clvl ? neg ? 0.50 ? 0.38 ? 0.25 v positive clamp level (i demag = +2.0 ma) clvl ? pos 0.50 0.72 0.85 v soft ? start section (note 7) ratio charge current/i ref (t a = ? 25 to +85 c) i ss ? ch /i ref 0.37 ? 0.43 ? discharge current (v soft ? start = 1.0 v) i discharge 1.5 5.0 ? ma clamp level v ss ? clvl 2.2 2.4 2.6 v circuit inhibition threshold (note 8) v ssinhi 30 ? 150 mv v cs soft ? start clamp level (r soft ? start = 5 k ) v cssoft ? start 0.45 0.5 0.55 v overvoltage section propagation delay (v cc > 18.1 v to v out low) t phl(in/out) 1.0 ? 4.0 s protection level on v cc (t a = ? 25 to +85 c) v cc prot 15.9 ? 18.1 v eht ovp section (note 9) negative clamp level (i synch ? in = ? 2.0 ma) neg ? syn c ? 0.65 ? 0.5 ? 0.35 v eht ovp input threshold v ref 7.0 7.4 7.8 v eht ovp input bias current (v eht ovp(pin 9) = 0 v) 9 i ehtovp ? 5.0 ? 0 a winding short circuit detection section wscd threshold with i pin15 = 200 a vshift 70 100 120 mv mpl & ohd section mpl parameter (note 10) mpl 0.185 0.240 0.295 v ? 1 mpl comparator threshold (note 11) v mpl ? th 2.4 2.5 2.6 v ohd parameter (note 12) ohd 1.15 1.50 1.85 v ? 1 ohd comparator threshold (note 13) v ohd ? th 2.4 2.5 2.6 v 5. adjust v cc above the startup threshold before setting to 12 v. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 6. this function can be inhibited by connecting pin 8 to gnd. in this case, there is a minimum off ? time equal to t dem ? gnd . 7. the mc44605 can be shut down by connecting soft ? start pin (pin 11) to gnd. 8. the circuit is shutdown if the soft ? start pin voltage is lower than this level. 9. this function can be inhibited by connecting pin 9 to gnd. in this case, the synchronization block is inhibited too and the m c44605 works in free mode. 10. this parameter is defined in the mpl . this parameter is ob tained by measuring the mpl pin average current and dividing thi s result by the corresponding squared v cs , the measured frequency value and the c t value deducted from the measured frequency value. measurement conditions: v feedback(pin 14) = 2.3 v, v soft ? start(pin 11) = 0.5 v and pins 7, 8, and 9 c onnected to gnd (the working frequency is typically equal to 18 khz ? r ref = 10 k 1%, c t = 2.2 nf). 11. the mpl comparator output is dis mpl . 12. this parameter is defined in the ohd . this parameter is obtained by measuring the ohd pin average current and dividing thi s result by the corresponding squared v cs value and multiplying it by the r ref value. measurement conditions: v feedback(pin 14) = 2.3 v, v soft ? start(pin 11) = 0.5 v and pins 7, 8, and 9 c onnected to gnd (the working frequency is typically equal to 18 khz ? r ref = 10 k 1%, c t = 2.2 nf). 13. the ohd comparator output is dis ohd . mc44605 http://onsemi.com 6 electrical characteristics (v cc and v c = 12 v, r ref = 10 k , c t = 2.2 nf, for typical values t a = 25 c, for min/max values t a = ? 25 to +85 c unless otherwise noted.) (note 14) characteristic pin # symbol min typ max unit disabling block section delay pulse width t wscd ? 4.0 ? s ratio (ehtovp and wscd disabling capacitor charge current)i ref i dis ? h /i ref 90 100 110 % ratio (mpl and ohd disabling capacitor charge current)i ref i dis ? l /i ref 2.7 3.1 3.5 % minimum v cc value enabling the disabling block latch (note 15) v ccdis 1.0 ? 5.0 v total device power supply current i cc ma startup ? up (v cc = 5.0 v with v cc increasing) ? 0.35 0.55 startup ? up (v cc = 9.0 v with v cc increasing) ? 0.35 0.55 startup ? up (v cc = 12 v with v cc increasing) ? 0.35 0.55 operating t a = ? 25 c to +85 c (note 16) ? 20 25 disabling mode (v cc = 6.0 v) (note 17) ? ? 0.55 power supply zener voltage (i cc = 35 ma) v z 18.5 ? ? v thermal shutdown ? ? 155 ? c 14. adjust v cc above the startup threshold before setting to 12 v. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 15. once a fault detection activated it, the di sabling block latch gets reset when the v cc becomes lower than this threshold. 16. refer to note 14. 17. this consumption is measured while the circuit is inhibited by the definitive latch. mc44605 http://onsemi.com 7 pin name pin description 1 v cc this pin is the positive supply of the ic. 2 v c the output high state, v oh , is set by the voltage applied to this pin. with a separate connection to the power source, it gives the possibility to set by means of an external resistor the output source current at a different value than the sink current. 3 output the output current capability is suited for driving a power mosfet. 4 gnd the ground pin is a single return typically connected back to the power source. it is used as control and power ground. 5 maximum power limitation this block enables to estimate the input power. when this calculated power is detected as too high, a fault information is sent to the disabling block in order to definitively disable the circuit. 6 over ? heating detection this block estimates the mosfet heating. when this calculated heating is too high, the device gets definitively disabled (disabling block action). 7 current sense input a voltage proportional to the current flowing into the power switch is connected to this input. the pwm latch uses this information to terminate the conduction of the output buffer. a maximum level of 1 v allows to limit the inductor current. 8 demagnetization detection a voltage delivered by an auxiliary transformer winding provides to the demagnetization pin an indication of the magnetization state of the flyback energy reservoir. a zero voltage detection corresponds to a complete core demagnetization. the demagnetization detection prevents the oscillator from a re ? start and so the circuit from a new conduction phase, if the fly ? back is not in a dead ? time state. this function can be inhibited by connecting pin 8 to gnd but in this case, there is a minimum off ? time typically equal to 3 s. 9 synchronization and e.h.t.ovp input activating the synchronization input pin with a pulse higher or equal to the negative threshold (typically ? 200 mv) allows the next switching period to be reinitialized. the oscillator is free when connecting pin 9 to gnd. when the e.h.t.ovp pin receives a voltage that is greater than 7.5 v, the disabling block c ext capacitor is charged so that the circuit gets definitively disabled if the c ext voltage becomes higher than v ref . this block is incorporated to detect and disable the device when the synchronization pulses are too high. 10 oscillator capacitor c t the free mode oscillator frequency is programmed by the capacitor c t choice together with the r ref resistance value. c t , connected between pin 10 and gnd, generates the oscillator sawtooth. 11 soft ? start a capacitor connected to this pin can temporary reduce the maximum inductor peak current. by this way, a soft ? start can be performed. by connecting pin 11 to ground, the mc44605 is shutdown. 12 c ext (disabling block) when a too high synchronization pulse voltage (e.h.t.ovp) or a winding short circuit (wscd) is detected, the capacitor c ext is charged using a current source i dis ? h . in the case of a mpl or ohd fault detection, c ext is charged using i dis ? l . if the c ext capacitor voltage gets higher than v ref , the circuit is definitively disabled. then, to re ? start, the converter must be switched off in order to make v cc decrease down to about 0 v. 13 e/a output the error amplifier output is made available for loop compensation. 14 voltage feedback this is the inverting input of the error amplifier. it can be connected to the switching mode power supply output through an optical (or else) feedback loop or to the subdivided v cc voltage in case of primary sensing technic. 15 winding short circuit detection programmation the w.s.c.d. block is incorporated to detect the transformer winding short circuits. this function is performed by detecting the inductor overcurrents thanks to a comparator which threshold is programmable to be well adapted to any application. 16 r ref the r ref value fixes the internal reference current that is particularly used to perform the precise oscillator waveform. the current range goes from 100 a up to 500 a. mc44605 http://onsemi.com 8 summary of the main design equations the following table consists of equations enabling to dimension a multisynchronized smps operating in discontinuous mode. pin max pout max pout max is the maximum power the load may draw in normal working. the maximum input power pin max is easily deducted by dividing pout max by the efficiency ( ). in this kind of application, the efficiency is generally taken equal to 80%. lp max 2 vac min nvo 2 vac min nvo 2 pin max fsync max 2 the inductor value lp must be chosen lower than lp max or ideally equal to this value (to optimize the application design ? in). in effect, if lp was higher than lp max , a synchronized and discontinuous working could not be guaranteed (in some cases, the demagnetization phase would not be finished while a new conduction phase should start to follow the synchronization). ipk max 2 pin max l fsync min ipk max is the maximum inductor peak current. this current is obtained when the power to transfer is maximum at the minimum synchronization frequency (60 w output, 30 khz in the proposed application). d max pin max lp fsync max vac min d max is the maximum duty cycle. the duty cycle is maximum at the lowest input voltage when the power demand is maximum while the synchronization frequency also is maximum. pon max 1 3 rds on ipk max 2 d max pon max is the maximum mosfet on ? time losses that are proportional to ipk max , d max and rds on (on ? time mosfet resistor). this conduction losses estimation enables to dimension the power mosfet. (v ds ) max 2 vac max (n vout) ( v ds )max is the maximum voltage the power switch must be able to face. in fact, this calculation does not take into account the turnings off spikes. so, it is necessary to take a margin of at least about 50 v. (v d ) max 2 vac max n vout (v d )max is the maximum voltage the high voltage secondary diode must be able to face. because of the turning off spikes, a margin must also be taken. (ni) max n n vout ipk max (a l ) and (ni) are the magnetic parameters. (ni) max must not exceed the ferrite (ni). otherwise, the transformer may get saturated when the peak current is high. a l l p (n n vout ) 2 (a l ) is the ferrite constant that links the primary inductor value to the squared number of primary turns: lp = a l x n p 2 . error amplifier a fully compensated error amplifier with access to the inverting input and output is provided. it features a typical dc voltage gain of 70 db. the non inverting input is internally biased at 2.5 v and is not pinned out. the converter output voltage is typically divided down and monitored by the inverting input. the maximum input bias current with the inverting input at 2.5 v is ? 2.0 a. this can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. + 1.0 ma 2.5 v figure 1. error amplifier compensation compensation r fb c f r 1 r 2 from power supply output r f 13 14 voltage feedback input error amplifier 2r r 1.0 v current sense comparator gnd 4 mc44605 mc44605 http://onsemi.com 9 the error amp output (pin 13) is provided for external loop compensation. the output voltage is offset by two diodes drops ( 1.4 v) and divided by three before it connects to the inverting input of the current sense comparator. this guarantees that no drive pulses appear at the source output (pin 3) when pin 13 is at its lowest state (v ol ). this occurs when the power supply is operating and the load is removed, or at the beginning of a soft ? start interval. the error amp minimum feedback resistance is limited by the amplifier?s minimum source current (0.2 ma) and the required output voltage (v oh ) to reach the current sense comparator?s 1.0 v clamp level: r1(min) (3 1v) 1.4 v 0.2 ma 22 k current sense comparator and pwm latch the mc44605 operates as a current mode controller. the circuit uses a current sense comparator to compare the inductor current to the threshold level established by the error amplifier output (pin 13). when the current reaches the threshold, the current sense comparator terminates the output switch conduction that has been initiated by the oscillator, by resetting the pwm latch. thus the error signal controls the peak inductor current on a cycle ? by ? cycle basis. this configuration ensures that only one single pulse appears at the source output during the appropriate oscillator cycle. figure 2. output totem pole r s q uvlo dis out v demag out thermal protection pwm latch current sense comparator substrate current sense 14 3 7 c r s r r 3 q1 v in v c r 2 vs the inductor current is converted to a voltage by inserting the ground referenced sense resistor r s in series with the power switch q1. this voltage is monitored by the current sense input (pin 7) and compared to a level derived from the error amp output. the peak inductor current under normal operating conditions is controlled by the voltage at pin 13 where: i pk v (pin13) 1.4 v 3 r s the current sense comparator threshold is internally clamped to 1.0 v. therefore the maximum peak switch current is: i pk(max) 1v r s undervoltage lockout section as depicted in figure 3, an undervoltage lockout has been incorporated to guarantee that the ic is fully functional before allowing the system working. in effect, the v cc is connected to the non inverting input of a comparator that has an upper threshold equal to 14.5 v (typical v stup ? th ) and a lower one equal to 7.5 v (typical v disable 2 ). this hysteresis comparator enables or disables the reference block that generates the voltage and current sources required by the system. this block particularly, produces v ref (pin 16 voltage) and i ref that is determined by the resistor r ref connected between pin 16 and the ground: i ref v ref r ref where v ref 2.5 v (typically) figure 3. v cc management reference block: voltage and current sources generator (v ref , i ref , ...) v ref enable c startup 10 1 0 v disable 7.5 v startup 14.5 v uvlo1 (to soft ? start) v disable1 9.0 v c uvlo1 r ref pin 16 mc44605 v cc (pin 1) in addition to this, v cc is compared to a second threshold level that is nearly equal to 9.0 v (v disable1 ) so that a signal uvlo1 is generated to reset the soft ? start block and so, to disable the output stage (refer to the soft ? start ) as soon as v cc becomes lower than v disable 1 . in this way, the circuit is reset and made ready for a next startup, before the reference block is disabled (refer to figure 3). thus, finally the upper limit for the minimum normal operating voltage mc44605 http://onsemi.com 10 is 9.4 v (maximum value of v disable 1 ) and so the minimum hysteresis is 4.2 v. [(v stup ? th ) min = 13.6 v]. the large hysteresis and the low startup current of the mc44605 make it ideally suited for off ? line converter applications where effic ient bootstrap startup techniques are required. soft ? start control section the v cs value is clamped down to the pin 11 voltage. so, if a capacitor is connected to this pin, its voltage increases slowly at the startup (the capacitor is charged by an internal current source 0.4 i ref ). so, v cs is limited during the startup and then a soft ? start is performed. this pin can be used to inhibit the circuit by applying a voltage that is lower than v ssinhi (refer to page 4). particularly, the mc44605 can be shutdown by connecting the soft ? start pin to ground. as soon as v dis1 is detected (that is v cc lower than v disable1 ), a signal uvlo1 is generated until the v cc falls down to v dis2 (refer to the undervoltage lockout section ). during the delay between the disable1 and the disable2, using a transistor controlled by uvlo1, the pin 11 voltage is made equal to zero in order to make the soft ? start arrangement ready to work for the next re ? start. figure 4. soft ? start mc44605 v ref uvlo1 soft start capacitor vcs 0.4 i ref v sslnhi output inhibition pin 11 2.4 v d z oscillator section (figures 5 & 5b) the oscillator and synchronization behavior is represented in figure 5b. the mc44605 oscillator achieves four functions: ? it fixes the free mode frequency ? it takes into account the synchronization signal ? it does not allow a new power switch conduction if the flyback is not in a dead ? time state when the circuit works in demagnetization mode (pin 8 connected) ? it builds the sf pulse required by the mpl block during the operating mode, the oscillator sawtooth can vary between a valley value (1.6 v typically) and a peak one (3.6 v typically) and presents three distinct phases: ? the c t charge ? the c t discharge ? the phase during which the oscillator voltage is maintained equal to its valley value. this happens at the end of a discharge cycle when the synchronization or demagnetization condition does not allow a new c t charge phase. during this sequence, i regul compensates the charge current i charge . the oscillator has two working modes: ? a free one when there is no synchronization ? a synchronized one. in the free working, the oscillator grows up from its valley value to its peak one for the charge phase and when once the peak value is reached, a discharge sequence makes the c t voltage decrease down to its valley value. when the decrease phase is finished, a new charge cycle occurs if the demagnetization condition is achieved (v dt high). otherwise there is a regul phase until v dt gets high. in the synchronized mode, the charge cycle is only allowed when the synchronization signal gets high while a dead time has been detected (v dt high). this charge phase is stopped when the synchronization signal has got low and when the oscillator voltage is higher than v int , the intermediary voltage level used to generate the calibrated pulse sf by comparing the c t voltage to this threshold. so, when these two conditions are performed, a discharge sequence is set until the oscillator voltage is equal to its valley value. then, the c t voltage is maintained constant thanks to the ?regul? arrangement until the next synchronization pulse. in both cases, during the charge phase, a signal v s is generated. when sf becomes high. v s gets high and remains in this state until the pwn latch is set of sf is low. then, v s keeps low until the next sf high level. this oscillator behavior is obtained using the process described in figure 5b. mc44605 http://onsemi.com 11 inductor current v dt sf output a ? free mode synchro input inductor current oscillator v int v dt b ? synchronized mode oscillator v int sf output figure 5b. oscillator behavior mc44605 http://onsemi.com 12 in effect, the output of the latch l1 is: ? high during the oscillator capacitor charge and during the regul phase ? low for the oscillator capacitor discharge now, the latch l2 is set when the l1 output is high and the synchronization condition is performed (that is: sync = 1 ? free mode or synchro signal high state) and during the dead ? time (v dt high). so, this latch is set for the c t charge. on the other hand, this latch is reset by the signal used to reset l1. consequently, it is reset at the end of the charge phase. so, in any case, q l2 is: ? high during the c t charge cycle ? low in the other cases thus, this latch enables to obtain a signal that is high for the charge phase and low in the other cases, whatever the mode (synchronized or free) and whatever the synchronization pulses width (higher than the delay necessary for the oscillator to reach its intermediary value or lower than this delay) in the synchronized mode. that is why: ? the discharge current source must be connected to the oscillator capacitor when q l1 is low. the condition (c t voltage higher than the valley value) is added to stop the discharge phase as soon as the oscillator voltage is detected as lower than the valley value (without any delay due to the l1 latch propagation time). ? the regul current source must be connected when: ? q l1 is high (charge or regul phase) ? q l2 is low (the oscillator is not in a charge phase) on the other hand, the oscillator charge is stopped when: ? the oscillator voltage reaches the peak value in the free mode ? the oscillator voltage is higher than the intermediary value (v int ) and the synchronization signal is negative, in the synchronized mode. consequently, in any case, q l2 that is high during the oscillator charge phase, is high for the delay during which the oscillator voltage grows from the valley value up to the intermediary one. that is why the signal sf (refer to the mpl block) that must be high when the oscillator voltage is between the valley value and the intermediary one during the charge phase (q l2 high), is obtained using an and gate with the following inputs: ?q l2 (q l2 high <=> charge phase) ?c oscint (c oscint high <=> the c t voltage is lower than the intermediary value). so, using the output of this and gate, sf is obtained. this signal sf is connected to a logic block consisting of two and gates and an or one. this block aims at supplying a signal vs that: ? gets high as soon as sf becomes high if the pwm latch output is low ? gets low as soon as the pwm latch is set and then remains low until the next cycle. figure 5. oscillator 10 c t vint 3.6 v v ref i charge c oscint c osc high c osc low 01 i regul disch q 10 i discharge sync & 1.6 v disch pwm latch output & & pwm latch set & vs c oscint r s l2 q q sf q l2 v dt (from demag block) & sync q r s l1 q disch & q l2 mc44605 c osc regul c t <1.6 v synchronization section (note 1) the synchronization block consists of a protection arrangement similar to the demagnetization block one (a diode + a negative active clamping system (note 2)). in addition to this, a high value resistor (r ? about 50 k ) is incorporated as the pin 9 input is also used by the ehtovp section. the signal obtained at the output of this protection arrangement, is compared to a negative threshold ( ? 200 mv, typically) so that when the synchronization pulse applied to the pin 9 (through a resistor or a resistors divider to adapt this input to the ehtovp function), is higher than this threshold, the system considers that the synchronization condition is performed (free mode or synchronization signal high level). note 1. the synchronization can be inhibited by connecting the pin 9 to the ground. by this means, a free mode is obtained. note 2. this negative active clamping system works even if the circuit is off. this feature is really useful as synchronization pulses may be applied while the product is off. mc44605 http://onsemi.com 13 figure 6. synchronization negative active clamping system pin 9 ? 200 mv r e.h.t. ovp block mc44605 v cc sync synchro. signal demagnetization section this block is incorporated to detect the complete core demagnetization in order to prevent the power mosfet from switching on if the converter is not in a dead time phase. that is why this block inhibits any oscillator re ? start as long as the inductor current is not finished (from the beginning of the on ? time to the end of the demagnetization phase). in a fly ? back, a good means to detect the demagnetization phase consists in using the v cc winding voltage. in effect, this voltage is: ? negative during the on ? time, ? positive during the off ? time, ? equal to zero for the dead ? time with generally a ringing (refer to figure 7). figure 7. demagnetization detection v pin 8 0.75 v 65 mv ? 0.33 v zero current detection on ? time off ? time dead ? time that is why, the mc44605 demagnetization detection consists of a comparator that compares the v cc winding voltage to a reference that is typically equal to 65 mv. a diode d is incorporated to clamp the positive applied voltages while an active clamping system limit the negative voltages to typically ? 0.33 v. this negative clamp level is high enough to avoid the substrate diode switching on. a latch system is incorporated to keep the demagnetization block output level low as soon as a voltage lower than 65 mv is detected and as long as a new restart is produced (high level on the output (refer to figure 8). this process avoids that any ringing on the signal used on the pin 8, disrupts the demagnetization detection (refer to figure 7). finally, this method results in a very accurate demagnetization phase detection, and the signal v dt drawn from this block is high only for the dead time. therefore, an oscillator re ? start and so, a new power switch conduction is only allowed during the dead ? time. for a higher safety, the v demagout output of the demagnetization block is also directly connected to the output, to disable it during the demagnetization phase (refer to the block diagram). the demagnetization detection can be inhibited by connecting pin 8 to the ground but in this case, a timer (about 3 s) that is incorporated to set the latch when it can not be set by v demagout , results in a minimum off ? time (refer to figure 8). figure 8. demagnetization block c dem oscillator output buffer r s q demag v cc negative active clamping system pin 8 d 65 mv v demag out 3 s q v dt overvoltage protection section the overvoltage arrangement compares a portion v cc to v ref (2.5 v) (refer to figure 9). in fact, this threshold corresponds to a v cc equal to to 17 v. when the v cc is higher than this level, the output is latched off until a new circuit re ? start. mc44605 http://onsemi.com 14 figure 9. overvoltage protection v cc v ref 0 t 2.5 v (v ref ) 2.5 v 5.0 s v ovp out 2.0 s (if v ovp out = 1.0, the output is disabled) in out delay enable c ovlo delay in out a delay (2 s) is incorporated in order to avoid any activation due to interferences by only taking into account the overvoltages that last at least 2 s. the v cc is connected when once the circuit has started ? up in order to limit the circuit startup consumption (t is switched on when once v ref has been generated). the overvoltage section is enabled 5 s after the regulator has started to allow the reference v ref to stabilize. e.h.t. overvoltage protection section this block uses the synchronization input as this section is incorporated to detect too high synchronization pulses and then to activate the device definitive latch in this case. figure 10. e.h.t. ovp negative active clamping system pin 9 2r synchronization block v cc disabling block synchro. pulses r1 r2 r e.h.t. ovp c ehtovp v ref mc44605 4 v this block consists of a high impedance resistors bridge (r is nearly equal to 50 k ? refer to figure 10) so that the ehtovp threshold is 7.5 v. so, using an external resistors bridge (r1, r2 < mc44605 http://onsemi.com 16 and: vcs r s ipk so: v mpl 2 r mpl mpl c t r 2 s l p pin a comparator is used to compare v mpl to v ref , the output of which, dis mpl , is connected to the ?definitive inhibition latch? of the disabling block. so, when the calculated power is higher than the threshold, the circuit is definitively disabled (the system considers that there is an overload condition). finally, replacing v mpl by 2.5 v (the threshold value), the r mpl value to be used, can be deducted: r mpl 1.25 l p mpl c t r 2 s (pin) max figure 14. ohd and mpl 2.5 v dis ohd v mpl disabling block 2.5 v v mpl dis mpl r ohd c ohd r mpl c mpl x vcs k mpl vcs 2 k ohd vcs 2 t ohd t mpl output mc44605 sf overheating detection section (o.h.d.) in the mpl block, the converter input power is calculated. in the o.h.d. block, that is the power mosfet heating which is calculated, using the following equation: p on 1 3 r dson ipk 2 d where: p on are the power switch on ? time losses r dson is the conduction mosfet resistor d is the duty cycle as in the mpl section, the squared ipk term is estimated by building a current source proportional to vcs 2 . the duty cycle is taken into account thanks to the action on this current source of a ?chopper? controlled by the circuit output. by this means, the pin 6 average current is proportional to the squared peak current multiplied to the duty cycle (refer to figure 14). so, using an external resistor and capacitor network (r ohd , c ohd ) on this pin, a voltage v ohd , proportional to the conduction losses can be obtained. like in the mpl block, this voltage v ohd , is compared to 2.5 v. if v ohd gets higher than this threshold, the disabling block is activated by dis ohd (output of the comparator). the external resistor r ohd choice enables to obtain a calculated v ohd equal to 2.5 v when the conduction losses are equal to their maximum value. in effect, v ohd r ohd k ohd vcs 2 d where: k ohd is the multiplier gain now, as k ohd that is depending on the reference current source i ref , is proportional to 1/r ref : k ohd k2 1 r ref where: k2 is a constant so: v ohd r ohd k2 vcs 2 r ref d finally: v ohd r ohd ohd vcs 2 d r ref where: ohd is the ohd parameter as defined in the specification. this is a constant equal to k2. now, as: vcs r s ipk so, replacing vcs and using the p on equation: v ohd 3 r ohd ohd r 2 s r ref r dson p on so, by choosing the value of r ohd , the heating corresponding to v ref is determined. if the mosfet dissipation is such that the heating is higher than this threshold, the ?definitive inhibition latch? of the disabling block is activated and so, the output gets definitively disabled. mc44605 http://onsemi.com 17 consequently, by replacing v ohd by 2.5 v (threshold value) in the last equation, the value r ohd to use, can be deducted: r ohd 2.5 r ref r dson 3 ohd r 2 s (p on ) max where: (p on ) max are the maximum on time losses that are acceptable. disabling block section this section consists of a ?definitive inhibition latch? (directly supplied by the v cc ) that disables the output (the output is forced to zero). in effect, this block aims at definitively disabling the circuit when one of the following faults is detected: ? a winding short circuit ? too high synchronization pulses ? a too high input power ? a too high power switch (mosfet) heating the signals corresponding to these faults are high when a fault is detected (for instance, when the input power is detected as too high, dis mpl is high). when one (or several) of these four faults is detected, a current source charges c ext (with a certain duty cycle) and when its voltage becomes higher than v ref , the definitive inhibition latch is activated. thus, the circuit gets definitively disabled after a delay depending on c ext . according to the detected fault, the current that charges c ext is not the same: the typical values are: ? 260 a for ehtovp and wscd ? 8.5 a for ohd and mpl when r ref is equal to 10 k . figure 15. disabling block 2.5 v dis ohd dis mpl r ext c ext v ref 3.4% i ref mc44605 pin 12 10 definitive inhibition latch v cc output buffer v ref 104% i ref e.h.t. ovp q s r v wscd delay 4 s 10 this latch is reset when the v cc falls down to about 3.0 v. in this case, if a new startup is performed, the circuit will work normally (until this fault or another one is detected). practically, to re ? start after a fault has shutdown the circuit, the converter must be turned off for a time long enough to enable the v cc capacitor discharge (repair time...). note: as v wscd is generally a really narrow pulse, it is necessary to add a latch and a delay to build a 4 s width pulse when v wscd becomes high. mc44605 http://onsemi.com 18 application schematic rfi filter 90 vac to 264 vac d1 ... d4 1n4007 v in 1.2 k 9 10 11 12 13 14 15 16 MC44605P c4....c7 1n4934 mr856 mta4n60e 33 nf laux 220 nf 1n4148 4.7 m 1nf/500v r1 1 / 5w 120 pf tl431 lp 8 7 6 5 4 3 2 1 1n4937 1n4937 1n4934 1n4934 2x150 k // 226 k 1n4733 270 10 k 100 nf moc8103 10 k 3.3 k 340 k 470 k 2.2 k 22 k 22 k 2.2 k 27 k 100 f 25 v 100 f 400 v 105 k 1 k 330 1 k 0.22 470 1n4937 4.7 f 1n4937 1nf / 1kv v in 1.8 m 100 f 100 f 470 f 1000 f 1000 f 3.6 k 100 k 100 k 10 k 1 f 2.2 nf sync 47 k 1 f 100 39 4.7 f 47 k / 2w 1nf 10 nf 1 nf 6.8 nf 470 pf 47 nf 160 v/0.1 a 70 v/0.2 a 40 v/0.5 a 1305 v/0.65 a 8 v/0.5 a 65 w output smps controlled by the mc44605 mains input range: 90 vac < ? > 264 vac synchronization range: 30 khz < ? > 100 khz orega transformer ref. g5984 ? 00 (lp = 195 h) mc44605 http://onsemi.com 19 performances input voltage 90 ? 260 vac synchronization range 30 to 100 khz outputs 160 v 100 ma 70 v 200 ma 40 v 500 ma 13.5 v 650 ma 8.0 v 500 ma measured efficiency (pout = 64 w) 30 khz 110 vac (input) 80% 220 vac 83% 60 khz 110 vac 81% 220 vac 82% 100 khz 110 vac 80% 220 vac 80% standby losses (no load ? pout = 0) 110 vac 2.0 w 220 vac 3.2 w ehtovp threshold 28 v maximum power limitation 30 khz 110 vac (input) 86 w (input) 220 vac 87 w 60 khz 110 vac 90 w 220 vac 95 w 100 khz 110 vac 94 w 220 vac 110 w overheating detection (pout = 64 w): the input rms levels at which the circuit detects an ohd case. 30 khz 85 v 60 khz 76 v 100 khz 76 v winding short circuit detection fully functional (tested by short circuiting one output diode or one transformer winding) mc44605 http://onsemi.com 20 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ? a ? b f c s h g d j l m 16 pl seating 18 9 16 k plane ? t ? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 pdip ? 16 case 648 ? 08 issue t on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 mc44605/d greenline is a trademark of motorola, inc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative |
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